WB32F10x Standard Peripherals Firmware Library

Data Fields
ITM_Type Struct Reference
Defines and Type Definitions » Instrumentation Trace Macrocell (ITM)

Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...

`#include <core_cm3.h>`

## Data Fields
union {
__OM uint8_t u8
__OM uint16_t u16
__OM uint32_t u32
} | PORT [32U]
uint32_t | RESERVED0 [864U]
__IOM uint32_t | TER
uint32_t | RESERVED1 [15U]
__IOM uint32_t | TPR
uint32_t | RESERVED2 [15U]
__IOM uint32_t | TCR
uint32_t | RESERVED3 [29U]
__OM uint32_t | IWR
__IM uint32_t | IRR
__IOM uint32_t | IMCR
uint32_t | RESERVED4 [43U]
__OM uint32_t | LAR
__IM uint32_t | LSR
uint32_t | RESERVED5 [6U]
__IM uint32_t | PID4
__IM uint32_t | PID5
__IM uint32_t | PID6
__IM uint32_t | PID7
__IM uint32_t | PID0
__IM uint32_t | PID1
__IM uint32_t | PID2
__IM uint32_t | PID3
__IM uint32_t | CID0
__IM uint32_t | CID1
__IM uint32_t | CID2
__IM uint32_t | CID3

## Detailed Description

Structure type to access the Instrumentation Trace Macrocell Register (ITM).

## Field Documentation

## ◆ CID0

__IM uint32_t CID0

Offset: 0xFF0 (R/ ) ITM Component Identification Register #0

## ◆ CID1

__IM uint32_t CID1

Offset: 0xFF4 (R/ ) ITM Component Identification Register #1

## ◆ CID2

__IM uint32_t CID2

Offset: 0xFF8 (R/ ) ITM Component Identification Register #2

## ◆ CID3

__IM uint32_t CID3

Offset: 0xFFC (R/ ) ITM Component Identification Register #3

## ◆ IMCR

__IOM uint32_t IMCR

Offset: 0xF00 (R/W) ITM Integration Mode Control Register

## ◆ IRR

__IM uint32_t IRR

Offset: 0xEFC (R/ ) ITM Integration Read Register

## ◆ IWR

__OM uint32_t IWR

Offset: 0xEF8 ( /W) ITM Integration Write Register

## ◆ LAR

__OM uint32_t LAR

Offset: 0xFB0 ( /W) ITM Lock Access Register

## ◆ LSR

__IM uint32_t LSR

Offset: 0xFB4 (R/ ) ITM Lock Status Register

## ◆ PID0

__IM uint32_t PID0

Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0

## ◆ PID1

__IM uint32_t PID1

Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1

## ◆ PID2

__IM uint32_t PID2

Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2

## ◆ PID3

__IM uint32_t PID3

Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3

## ◆ PID4

__IM uint32_t PID4

Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4

## ◆ PID5

__IM uint32_t PID5

Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5

## ◆ PID6

__IM uint32_t PID6

Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6

## ◆ PID7

__IM uint32_t PID7

Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7

## ◆ PORT

__OM { ... } PORT[32U]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

## ◆ TCR

__IOM uint32_t TCR

Offset: 0xE80 (R/W) ITM Trace Control Register

## ◆ TER

__IOM uint32_t TER

Offset: 0xE00 (R/W) ITM Trace Enable Register

## ◆ TPR

__IOM uint32_t TPR

Offset: 0xE40 (R/W) ITM Trace Privilege Register

## ◆ u16

__OM uint16_t u16

Offset: 0x000 ( /W) ITM Stimulus Port 16-bit

## ◆ u32

__OM uint32_t u32

Offset: 0x000 ( /W) ITM Stimulus Port 32-bit

## ◆ u8

__OM uint8_t u8

Offset: 0x000 ( /W) ITM Stimulus Port 8-bit

The documentation for this struct was generated from the following file:

- core_cm3.h